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iso7420e , iso7420fe , iso7421e , iso7421fe sllse45f ? december 2010 ? revised july 2015 iso742x low-power dual channel digital isolators 1 features 3 description iso742x provide galvanic isolation up to 2500 v rms 1 ? signaling rate > 50 mbps for 1 minute per ul and 4242 v pk per vde. these ? default output 'high' and 'low' options devices have two isolated channels. each channel ? low power consumption: typical i cc per channel has a logic input and output buffer separated by a (3.3-v supplies): silicon dioxide (sio 2 ) insulation barrier. used in conjunction with isolated power supplies, these ? iso7420: 1.4 ma at 1 mbps, 2.5 ma at devices prevent noise currents on a data bus or other 25 mbps circuit from entering the local ground and interfering ? iso7421: 1.8 ma at 1 mbps, 2.8 ma at with or damaging sensitive circuitry. iso7420 has 25 mbps both channels in the same direction while iso7421 has the two channels in opposite direction. in case of ? low propagation delay: 7 ns typical input power or signal loss, default output is ' low ' for ? low pulse skew: 200 ps typical devices with suffix ' f ' and ' high ' for devices without ? wide t a range specified: ? 40 c to 125 c suffix ' f ' . iso742x have no integrated noise filter and ? 50-kv/ s transient immunity, typical thus have fast propagation delays. ? isolation barrier life: > 25 years these devices have ttl input thresholds and ? operates from 3-v to 5.5-v supply levels operate from 3-v to 5.5-v supplies. all inputs are 5-v tolerant when supplied from a 3.3-v supply. ? 3.3-v and 5-v level translation ? narrow body soic-8 package device information (1) ? safety and regulatory approvals: part number package body size (nom) ? 4242 v pk isolation per din v vde v 0884-10 iso7420e and din en 61010-1 iso7420fe soic (8) 4.90 mm x 3.91 mm ? 2500 v rms isolation for 1 minute per ul 1577 iso7421e ? csa component acceptance notice 5a, iec iso7421fe 60950-1 and iec 61010-1 standards (1) for all available packages, see the orderable addendum at the end of the datasheet. ? cqc certification per gb4943.1-2011 ? simplified schematic 2 applications ? opto-coupler replacement in: ? industrial fieldbus ? profibus ? modbus ? devicenet ? data buses ? servo control interface ? motor control v cci and gndi are supply and ground connections respectively for the input ? power supplies channels. ? battery packs v cco and gndo are supply and ground connections respectively for the output channels. 1 an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. outx gndo gndi inx v cco v cci isolation capacitor productfolder sample &buy technical documents tools & software support &community
iso7420e , iso7420fe , iso7421e , iso7421fe sllse45f ? december 2010 ? revised july 2015 www.ti.com table of contents 10% .......................................................................... 11 1 features .................................................................. 1 6.14 typical characteristics .......................................... 12 2 applications ........................................................... 1 7 parameter measurement information ................ 15 3 description ............................................................. 1 8 detailed description ............................................ 16 4 revision history ..................................................... 2 8.1 overview ................................................................. 16 5 pin configuration and functions ......................... 4 8.2 functional block diagram ....................................... 16 6 specifications ......................................................... 5 8.3 feature description ................................................. 17 6.1 absolute maximum ratings ..................................... 5 8.4 device functional modes ........................................ 20 6.2 esd ratings .............................................................. 5 9 applications and implementation ...................... 21 6.3 recommended operating conditions ....................... 5 9.1 application information ............................................ 21 6.4 thermal information .................................................. 5 9.2 typical application ................................................. 21 6.5 electrical characteristics: v cc1 and v cc2 = 5 v 10% ............................................................................ 6 10 power supply recommendations ..................... 24 6.6 electrical characteristics: v cc1 = 5 v 10%, v cc2 = 11 layout ................................................................... 25 3.3 v 10% ............................................................... 7 11.1 layout guidelines ................................................. 25 6.7 electrical characteristics: v cc1 = 3.3 v 10%, v cc2 11.2 layout example .................................................... 25 = 5 v 10% ............................................................... 8 12 device and documentation support ................. 26 6.8 electrical characteristics: v cc1 and v cc2 = 3.3 v 12.1 documentation support ........................................ 26 10% ............................................................................ 9 12.2 related links ........................................................ 26 6.9 power dissipation characteristics ............................ 9 12.3 community resources .......................................... 26 6.10 switching characteristics: v cc1 and v cc2 = 5 v 12.4 trademarks ........................................................... 26 10% .......................................................................... 10 12.5 electrostatic discharge caution ............................ 26 6.11 switching characteristics: v cc1 = 5 v 10%, v cc2 = 3.3 v 10% .......................................................... 10 12.6 glossary ................................................................ 26 6.12 switching characteristics: v cc1 = 3.3 v 10%, 13 mechanical, packaging, and orderable v cc2 = 5 v 10% .................................................... 11 information ........................................................... 26 6.13 switching characteristics: v cc1 and v cc2 = 3.3 v 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision e (january 2013) to revision f page ? changed the datasheet format to the new ti standard .......................................................................................................... 1 ? added pin configuration and functions section, esd ratings table, feature description section, device functional modes , application and implementation section, power supply recommendations section, layout section, device and documentation support section, and mechanical, packaging, and orderable information section .............................. 1 ? deleted text from the description: " cc-grade devices have integrated 10ns-filters for harsh environments where short noise pulses may be present at the device input pins. " ................................................................................................ 1 ? vde standard changed to din v vde v 0884-10 (vde v 0884-10):2006-12 ...................................................................... 1 ? deleted cc-grade from t plh , t phl in the switching characteristics table .............................................................................. 10 ? deleted cc-grade from t plh , t phl in the switching characteristics table .............................................................................. 10 ? deleted cc-grade from t plh , t phl in the switching characteristics table .............................................................................. 11 ? deleted cc-grade from t plh , t phl in the switching characteristics table .............................................................................. 11 ? changed the available options table to the feature description table ............................................................................. 17 changes from revision d (december 2011) to revision e page ? deleted devices iso7420fcc and iso7421fcc .................................................................................................................. 1 ? changed the note: text ...................................................................................................................................................... 17 ? added table note to v iorm .................................................................................................................................................... 18 ? changed z to undetermined for the output outa, outb column of the function table ....................................... 20 2 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: iso7420e iso7420fe iso7421e iso7421fe
iso7420e , iso7420fe , iso7421e , iso7421fe www.ti.com sllse45f ? december 2010 ? revised july 2015 changes from revision c (march 2011) to revision d page ? changed safety feature bullet from: ul 1577 approved; other approvals pending to: all agencies approvals completed .............................................................................................................................................................................. 1 ? changed the regulatory information table ............................................................................................................ 18 changes from revision b (january 2011) to revision c page ? added devices iso7420fcc and iso7421fcc .................................................................................................................... 1 ? changed feature bullet to: low propagation delay: 7 ns typical (e-grade) ....................................................................... 1 ? changed feature bullet to: low pulse skew: 200 typical (e-grade) ................................................................................... 1 ? changed the safety and regulatory approvals list ............................................................................................... 1 ? changed the data sheet description................................................................................................................................ 1 ? changed the supply current values for iso7421x at 10, 25, and 50 mbps .......................................................................... 6 ? changed the supply current values for iso7421x at 10, 25, and 50 mbps .......................................................................... 7 ? changed the supply current values for iso7421x at 10, 25, and 50 mbps .......................................................................... 8 ? changed the supply current values for iso7421x 25 and 50 mbps ..................................................................................... 9 ? added cc-grade and valued to t plh , t phl in the switching characteristics table ................................................................. 10 ? added iso7421x values for pulse width distortion, channel-to-channel output skew time, and part-to-part skew time .... 10 ? added cc-grade and valued to t plh , t phl in the switching characteristics table ................................................................. 10 ? added iso7421x values for pulse width distortion and channel-to-channel output skew time ........................................... 10 ? added cc-grade and valued to t plh , t phl in the switching characteristics table ................................................................. 11 ? added cc-grade and valued to t plh , t phl in the switching characteristics table ................................................................. 11 ? added graphs figure 5 , figure 6 , figure 7 , and figure 8 .................................................................................................... 12 ? added graphs figure 14 and figure 15 ................................................................................................................................ 13 ? changed note 1 figure 16 ................................................................................................................................................... 15 ? changed figure 17 ............................................................................................................................................................... 15 ? changed the available options table .................................................................................................................................. 17 ? changed isolation resistance test conditions ....................................................................................................................... 17 ? changed the values of v iorm and v pr in the insulation characteristics table ..................................................... 18 ? changed the value of v iotm in the insulation characteristics table from: 4000 to: 4242 .................................. 18 ? changed figure 21 ............................................................................................................................................................... 19 ? changed pu to x in the last row of the function table ................................................................................................ 20 ? added section: supply current equations .............................................................................................................. 22 changes from revision a (december 2010) to revision b page ? changed feature bullet from: iso7421: tbdma at 1mbps, tbdma at 25mbps to: iso7421: 1.8ma at 1mbps, 2.8ma at 25mbps ................................................................................................................................................................... 1 ? updated the iso7421x supply current values for v cc1 and v cc2 = 5v ................................................................................. 6 ? updated the iso7421x supply current values for v cc1 = 5v and v cc2 = 3.3v ..................................................................... 7 ? updated the iso7421x supply current values for v cc1 = 3.3v and v cc2 = 5v ..................................................................... 8 ? updated the iso7421x supply current values for v cc1 and v cc2 = 3.3v .............................................................................. 9 changes from original (december 2010) to revision a page ? changed the max values for supply current for v cc1 and v cc2 , c l = 15pf ........................................................................... 9 copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 3 product folder links: iso7420e iso7420fe iso7421e iso7421fe
iso7420e , iso7420fe , iso7421e , iso7421fe sllse45f ? december 2010 ? revised july 2015 www.ti.com 5 pin configuration and functions iso7420 d package iso7421 d package 8-pin soic 8-pin soic top view top view pin functions pin i/o description name iso7420x iso7421x ina 2 7 i input, channel a inb 3 3 i input, channel b gnd1 4 4 ? ground connection for v cc1 gnd2 5 5 ? ground connection for v cc2 outa 7 2 o output, channel a outb 6 6 o output, channel b v cc1 1 1 ? power supply, v cc1 v cc2 8 8 ? power supply, v cc2 4 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: iso7420e iso7420fe iso7421e iso7421fe v cc1 outa inb gnd1 v cc2 ina outb gnd2 12 3 4 8 7 6 5 isolation v cc1 ina inb gnd1 v cc2 outa outb gnd2 12 3 4 8 7 6 5 isolation
iso7420e , iso7420fe , iso7421e , iso7421fe www.ti.com sllse45f ? december 2010 ? revised july 2015 6 specifications 6.1 absolute maximum ratings (1) min max unit v cc supply voltage (2) , v cc1 , v cc2 ? 0.5 6 v v i voltage at in, out ? 0.5 v cc + 0.5 (3) v i o output current 15 ma v srg maximum surge immunity - supports iec 61000-4-5 4000 v pk t j(max) maximum junction temperature 150 c t stg storage temperature ? 65 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to network ground terminal and are peak voltage values. (3) maximum voltage must not exceed 6 v. 6.2 esd ratings value unit human body model (hbm), per ansi/esda/jedec js-001 (1) 3000 v (esd) electrostatic discharge charged-device model (cdm), per jedec specification jesd22-c101 (2) 1500 v machine model (mm) ansi/esds5.2-1996 200 (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.3 recommended operating conditions min nom max unit v cc1 , v cc2 supply voltage 3.0 5.5 v i oh high-level output current ? 4 ma i ol low-level output current 4 ma v ih high-level input voltage 2 5.5 v v il low-level input voltage 0 0.8 v t ui input pulse duration 20 ns 1 / t ui signaling rate 0 50 (1) mbps t j (2) junction temperature ? 40 136 c t a ambient temperature -40 25 125 c (1) under typical conditions, these devices are capable of signaling rate > 150 mbps. (2) to maintain the recommended operating conditions for t j , see the thermal information table. 6.4 thermal information iso742x thermal metric (1) d (soic) unit 8 pins r ja low-k board 212 junction-to-ambient thermal c/w resistance high-k board 116.6 r jc(top) junction-to-case (top) thermal resistance 71.6 c/w r jb junction-to-board thermal resistance 57.3 c/w jt junction-to-top characterization parameter 28.3 c/w jb junction-to-board characterization parameter 56.8 c/w (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report, spra953 . copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 5 product folder links: iso7420e iso7420fe iso7421e iso7421fe
iso7420e , iso7420fe , iso7421e , iso7421fe sllse45f ? december 2010 ? revised july 2015 www.ti.com 6.5 electrical characteristics: v cc1 and v cc2 = 5 v 10% t a = ? 40 c to 125 c parameter test conditions min typ max unit i oh = ? 4 ma; see figure 16 . v cco (1) ? 0.8 4.6 v oh high-level output voltage v i oh = ? 20 a; see figure 16 . v cco ? 0.1 5 i ol = 4 ma; see figure 16 . 0.2 0.4 v ol low-level output voltage v i ol = 20 a; see figure 16 . 0 0.1 v i(hys) input threshold voltage hysteresis 400 mv i ih high-level input current 10 a inx at 0 v or v cci (1) i il low-level input current ? 10 a cmti common-mode transient immunity v i = v cci or 0 v; see figure 18 . 25 50 kv/ s supply current (all inputs switching with square wave clock signal for dynamic i cc measurement) iso7420x i cc1 0.4 0.8 dc input: v i = v cci or 0 v, dc to 1 mbps ac input: c l = 15 pf i cc2 3.4 5 i cc1 0.6 1 10 mbps i cc2 4.5 6 supply current for v cc1 and v cc2 ma i cc1 1 1.5 25 mbps c l = 15 pf i cc2 6.2 8 i cc1 1.7 2.5 50 mbps i cc2 9 12 iso7421x i cc1 2.3 3.6 dc input: v i = v cci or 0 v, dc to 1 mbps ac input: c l = 15 pf i cc2 2.3 3.6 i cc1 2.9 4.5 10 mbps i cc2 2.9 4.5 supply current for v cc1 and v cc2 ma i cc1 4.3 6 25 mbps c l = 15 pf i cc2 4.3 6 i cc1 6 8.5 50 mbps i cc2 6 8.5 (1) v cci = input-side v cc ; v cco = output-side v cc 6 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: iso7420e iso7420fe iso7421e iso7421fe
iso7420e , iso7420fe , iso7421e , iso7421fe www.ti.com sllse45f ? december 2010 ? revised july 2015 6.6 electrical characteristics: v cc1 = 5 v 10%, v cc2 = 3.3 v 10% t a = ? 40 c to 125 c parameter test conditions min typ max unit i oh = ? 4 ma; iso7421x (5-v side) v cc1 ? 0.8 4.6 see figure 16 . iso7420x/7421x (3.3-v side) v cc2 - 0.4 3 v oh high-level output voltage v i oh = ? 20 a; iso7421x (5-v side) v cc1 ? 0.1 5 see figure 16 , iso7420x/7421x (3.3-v side) v cc2 ? 0.1 3.3 i ol = 4 ma; see figure 16 . 0.2 0.4 v ol low-level output voltage v i ol = 20 a; see figure 16 . 0 0.1 v i(hys) input threshold voltage hysteresis 400 mv i ih high-level input current 10 a inx at 0 v or v cci i il low-level input current ? 10 a cmti common-mode transient immunity v i = v cci or 0 v; see figure 18 . 25 50 kv/ s supply current (all inputs switching with square wave clock signal for dynamic i cc measurement) iso7420x i cc1 0.4 0.8 dc input: v i = v cci or 0 v, dc to 1 mbps ac input: c l = 15 pf i cc2 2.6 3.7 i cc1 0.6 1 10 mbps i cc2 3.3 4.3 supply current for v cc1 and v cc2 ma i cc1 1 1.5 25 mbps c l = 15 pf i cc2 4.4 5.6 i cc1 1.7 2.5 50 mbps i cc2 6.2 7.5 iso7421x i cc1 2.3 3.6 dc input: v i = v cci or 0 v, dc to 1 mbps ac input: c l = 15 pf i cc2 1.8 2.8 i cc1 2.9 4.5 10 mbps i cc2 2.2 3.2 supply current for v cc1 and v cc2 ma i cc1 4.3 6 25 mbps c l = 15 pf i cc2 2.8 4.1 i cc1 6 8.5 50 mbps i cc2 3.8 5.5 copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 7 product folder links: iso7420e iso7420fe iso7421e iso7421fe
iso7420e , iso7420fe , iso7421e , iso7421fe sllse45f ? december 2010 ? revised july 2015 www.ti.com 6.7 electrical characteristics: v cc1 = 3.3 v 10%, v cc2 = 5 v 10% t a = ? 40 c to 125 c parameter test conditions min typ max unit iso7421x (3.3-v side) v cc1 ? 0.4 3 i oh = ? 4 ma; see figure 16 . iso7420x/7421x (5-v side) v cc2 ? 0.8 4.6 v oh high-level output voltage v iso7421x (3.3-v side) v cc1 ? 0.1 3.3 i oh = ? 20 a; see figure 16 iso7420x/7421x (5-v side) v cc2 ? 0.1 5 i ol = 4 ma; see figure 16 . 0.2 0.4 v ol low-level output voltage v i ol = 20 a; see figure 16 . 0 0.1 v i(hys) input threshold voltage hysteresis 400 mv i ih high-level input current 10 a inx at 0 v or v cci i il low-level input current ? 10 a cmti common-mode transient immunity v i = v cci or 0 v; see figure 18 . 25 50 kv/ s supply current (all inputs switching with square wave clock signal for dynamic i cc measurement) iso7420x i cc1 0.2 0.4 dc input: v i = v cci or 0 v, dc to 1 mbps ac input: c l = 15 pf i cc2 3.4 5 i cc1 0.4 0.6 10 mbps i cc2 4.5 6 supply current for v cc1 and v cc2 ma i cc1 0.6 0.9 25 mbps c l = 15 pf i cc2 6.2 8 i cc1 1 1.3 50 mbps i cc2 9 12 iso7421x i cc1 1.8 2.8 dc input: v i = v cci or 0 v, dc to 1 mbps ac input: c l = 15 pf i cc2 2.3 3.6 i cc1 2.2 3.2 10 mbps i cc2 2.9 4.5 supply current for v cc2 and v cc2 ma i cc1 2.8 4.1 25 mbps c l = 15 pf i cc2 4.3 6 i cc1 3.8 5.5 50 mbps i cc2 6 8.5 8 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: iso7420e iso7420fe iso7421e iso7421fe
iso7420e , iso7420fe , iso7421e , iso7421fe www.ti.com sllse45f ? december 2010 ? revised july 2015 6.8 electrical characteristics: v cc1 and v cc2 = 3.3 v 10% t a = ? 40 c to 125 c parameter test conditions min typ max unit i oh = ? 4 ma; see figure 16 . v cco (1) ? 0.4 3 v oh high-level output voltage v i oh = ? 20 a; see figure 16 . v cco ? 0.1 3.3 i ol = 4 ma; see figure 16 . 0.2 0.4 v ol low-level output voltage v i ol = 20 a; see figure 16 . 0 0.1 v i(hys) input threshold voltage hysteresis 400 mv i ih high-level input current 10 a inx at 0 v or v cci (1) i il low-level input current ? 10 a cmti common-mode transient immunity v i = v cci or 0 v; see figure 18 . 25 50 kv/ s supply current (all inputs switching with square wave clock signal for dynamic i cc measurement) iso7420x i cc1 0.2 0.4 dc input: v i = v cci or 0 v, dc to 1 mbps ac input: c l = 15 pf i cc2 2.6 3.7 i cc1 0.4 0.6 10 mbps i cc2 3.3 4.3 supply current for v cc1 and v cc2 ma i cc1 0.6 0.9 25 mbps c l = 15 pf i cc2 4.4 5.6 i cc1 1 1.3 50 mbps i cc2 6.2 7.5 iso7421x i cc1 1.8 2.8 dc input: v i = v cci or 0 v, dc to 1 mbps ac input: c l = 15 pf i cc2 1.8 2.8 i cc1 2.2 3.2 10 mbps i cc2 2.2 3.2 supply current for v cc2 and v cc2 ma i cc1 2.8 4.1 25 mbps c l = 15 pf i cc2 2.8 4.1 i cc1 3.8 5.5 50 mbps i cc2 3.8 5.5 (1) v cci = input-side v cc ; v cco = output-side v cc 6.9 power dissipation characteristics iso742x thermal metric d (soic) unit 8 pins v cc1 = v cc2 = 5.5 v, t j = 150 c, c l = 15 pf, p d device power dissipation 138 mw input a 100-mbps 50% duty-cycle square wave copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 9 product folder links: iso7420e iso7420fe iso7421e iso7421fe
iso7420e , iso7420fe , iso7421e , iso7421fe sllse45f ? december 2010 ? revised july 2015 www.ti.com 6.10 switching characteristics: v cc1 and v cc2 = 5 v 10% t a = ? 40 c to 125 c parameter test conditions min typ max unit t plh , t phl propagation delay time 7 11 ns iso7420x see figure 16 . 0.2 3 pwd (1) pulse width distortion |t phl ? t plh | ns iso7421x 0.3 3.7 iso7420x 0.3 1 t sk(o) (2) channel-to-channel output skew time ns iso7421x 0.3 2 iso7420x 3.7 t sk(pp) (3) part-to-part skew time ns iso7421x 4.9 t r output signal rise time 1.8 ns see figure 16 . t f output signal fall time 1.7 ns t fs fail-safe output delay time from input power loss see figure 17 . 6 s (1) also known as pulse skew. (2) t sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. (3) t sk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. 6.11 switching characteristics: v cc1 = 5 v 10%, v cc2 = 3.3 v 10% t a = ? 40 c to 125 c parameter test conditions min typ max unit t plh , t phl propagation delay time 8 13.5 ns iso7420x see figure 16 . 0.3 3 pwd (1) pulse width distortion |t phl ? t plh | ns iso7421x 0.5 5.6 iso7420x 1.5 t sk(o) (2) channel-to-channel output skew time ns iso7421x 0.5 3 iso7420x 5.4 t sk(pp) (3) part-to-part skew time ns iso7421x 6.3 t r output signal rise time 2 ns see figure 16 . t f output signal fall time 2 ns t fs fail-safe output delay time from input power loss see figure 17 . 6 s (1) also known as pulse skew. (2) t sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. (3) t sk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. 10 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: iso7420e iso7420fe iso7421e iso7421fe
iso7420e , iso7420fe , iso7421e , iso7421fe www.ti.com sllse45f ? december 2010 ? revised july 2015 6.12 switching characteristics: v cc1 = 3.3 v 10%, v cc2 = 5 v 10% t a = ? 40 c to 125 c parameter test conditions min typ max unit iso7420x 7.5 12 t plh , t phl propagation delay time ns iso7421x 7.5 14 see figure 16 . iso7420x 0.7 3 pwd (1) pulse width distortion |t phl ? t plh | ns iso7421x 0.7 3.6 iso7420x 0.5 1.5 t sk(o) (2) channel-to-channel output skew time ns iso7421x 0.5 3 iso7420x 4.6 t sk(pp) (3) part-to-part skew time ns iso7421x 8.5 t r output signal rise time 1.7 ns see figure 16 . t f output signal fall time 1.6 ns t fs fail-safe output delay time from input power loss see figure 17 . 6 s (1) also known as pulse skew. (2) t sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. (3) t sk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. 6.13 switching characteristics: v cc1 and v cc2 = 3.3 v 10% t a = ? 40 c to 125 c parameter test conditions min typ max unit t plh , t phl propagation delay time 8.5 14 ns see figure 16 pwd (1) pulse width distortion |t phl ? t plh | iso7420x and iso7421x 0.5 2 ns iso7420x 0.4 2 t sk(o) (2) channel-to-channel output skew time ns iso7421x 0.4 3 iso7420x 6.2 t sk(pp) (3) part-to-part skew time ns iso7421x 6.8 t r output signal rise time 2 ns see figure 16 t f output signal fall time 1.8 ns t fs fail-safe output delay time from input power loss see figure 17 6 s (1) also known as pulse skew. (2) t sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. (3) t sk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 11 product folder links: iso7420e iso7420fe iso7421e iso7421fe
iso7420e , iso7420fe , iso7421e , iso7421fe sllse45f ? december 2010 ? revised july 2015 www.ti.com 6.14 typical characteristics figure 2. iso7420 supply current both channels vs data figure 1. iso7420 supply current per channel vs data rate rate (no load) (no load) figure 3. iso7420 supply current per channel vs data rate figure 4. iso7420 supply current both channels vs data (15 pf load) rate (15 pf load) figure 5. iso7421 supply current per channel vs data rate figure 6. iso7421 supply current both channels vs data (no load) rate (no load) 12 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: iso7420e iso7420fe iso7421e iso7421fe 0 20 40 60 80 100 120 data rate - mbps 0 1 2 3 4 5 6 7 8 supply current - ma i and cc1 i at 5 v cc2 i and cc1 i at 3.3 v cc2 t = 25 c a o no load i and cc1 i at 5 v cc2 i and cc1 i at 3.3 v cc2 0 20 40 60 80 100 120 data rate - mbps 0 0.5 1 1.5 2 2.5 3 3.5 4 supply current - ma t = 25 c a o no load i at 5 v cc2 i at 3.3 v cc2 i at 5 v cc1 i at 3.3 v cc1 0 20 40 60 80 100 120 data rate - mbps 0 1 2 3 4 5 6 7 8 supply current - ma t = 25 c a o c = 15 pf load l i at 5 v cc2 i at 3.3 v cc2 i at 5 v cc1 i at 3.3 v cc1 0 20 40 60 80 100 120 data rate - mbps 0 2 4 6 8 10 12 14 16 supply current - ma t = 25 c a o c = 15 pf load l 0 20 40 60 80 100 120 data rate - mbps 0 1 2 3 4 5 6 supply current - ma i at 5 v cc2 i at 3.3 v cc2 i at 3.3 v cc1 i at 5 v cc1 t = 25 c no load a o 0 20 40 60 80 100 120 data rate - mbps i at 5 v cc2 i at 3.3 v cc2 i at 5 v cc1 i at 3.3 v cc1 0 2 4 6 8 10 12 supply current - ma t = 25 c no load a o
iso7420e , iso7420fe , iso7421e , iso7421fe www.ti.com sllse45f ? december 2010 ? revised july 2015 typical characteristics (continued) figure 7. iso7421 supply current per channel vs data rate figure 8. iso7421 supply current both channels vs data (15 pf load) rate (15 pf load) figure 9. propagation delay time vs free-air temperature figure 10. propagation delay time vs free-air temperature figure 11. input v cc fail-safe voltage threshold vs free-air figure 12. high-level output voltage vs high-level output temperature current copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 13 product folder links: iso7420e iso7420fe iso7421e iso7421fe 0 1 2 3 4 5 6 -80 -70 -60 -50 -40 -30 -20 -10 0 i - high-level output current - ma oh v - high-level output voltage - v oh output v = 3.3 v cc t = 25c a output v = 5 v cc fs+ fs- -50 -25 0 25 50 75 100 125 150 t - free-air temperature - c a 2.4 2.45 2.5 2.55 2.6 2.65 2.7 fail-safe voltage threshold - v -50 -25 0 25 50 75 100 125 150 t - free-air temperature - c a 7.5 8 8.5 9 9.5 10 10.5 t - propagation delay time - ns pd t plh t phl v = v = 3.3 v, c = 15 pf cc1 cc2 l -50 -25 0 25 50 75 100 125 150 t - free-air temperature - c a 6 6.5 7 7.5 8 t - propagation delay time - ns pd t plh t phl v = v = 5 v, c = 15 pf cc1 cc2 l 0 20 40 60 80 100 120 data rate - mbps 0 1 2 3 4 5 6 8 supply current - ma 9 10 7 i and cc1 i at 5 v cc2 i and cc1 i at 3.3 v cc2 t = 25 c c a o l 15 pf 0 20 40 60 80 100 120 data rate - mbps 0 1 2 3 4 5 6 7 supply current - ma i and cc1 i at 5 v cc2 i and cc1 i at 3.3 v cc2 t = 25 c c a o 15 pf l
iso7420e , iso7420fe , iso7421e , iso7421fe sllse45f ? december 2010 ? revised july 2015 www.ti.com typical characteristics (continued) figure 13. low-level output voltage vs low-level output figure 14. iso7420fe output jitter vs data rate current figure 15. iso7421fe output jitter vs data rate 14 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: iso7420e iso7420fe iso7421e iso7421fe 0 20 40 60 80 100 120 data rate - mbps 0 0.4 output jitter (pk-pk) - ns 1.4 1 outa and outb, 5v-oper. outa and outb, 3.3v-oper. 0.2 1.20.6 0.8 t = 25 c c a o l 15 pf 1.6 0 1 2 3 4 5 6 v - low-level output voltage - v ol 0 10 20 30 40 50 60 70 i - low-level output current - ma ol output v = 3.3 v cc output v = 5 v cc t = 25c a 0 20 40 60 80 100 120 data rate - mbps 0 0.4 output jitter (pk-pk) - ns 1.4 1 outa and outb, 5v-oper. t = 25 c c a o l 15 pf outa and outb, 3.3v-oper. 0.2 1.20.6 0.8
iso7420e , iso7420fe , iso7421e , iso7421fe www.ti.com sllse45f ? december 2010 ? revised july 2015 7 parameter measurement information (1) the input pulse is supplied by a generator having the following characteristics: prr 50 khz, 50% duty cycle, t r 3 ns, t f 3 ns, z o = 50 ? . at the input, a 50- resistor is required to terminate the input generator signal. it is not needed in an actual application. (2) c l = 15 pf and includes instrumentation and fixture capacitance within 20%. figure 16. switching characteristic test circuit and voltage waveforms (1) c l = 15 pf and includes instrumentation and fixture capacitance within 20%. figure 17. fail-safe output delay-time test circuit and voltage waveforms (1) c l = 15 pf and includes instrumentation and fixture capacitance within 20%. figure 18. common-mode transient immunity test circuit copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 15 product folder links: iso7420e iso7420fe iso7421e iso7421fe isolation barrier c = 0.1 f 1% in v oh or v ol out v cci + C v c m v cco c = 0.1 f 1% ! gndo gndi s1 + C pass-fail criteria C output must remainstable. c l ! (1) v o out in in = 0 v (devices without suffix f) in = v (devices with suffix f) cc (1) c l v i 0 v t fs fs high v o v i 2.7 v 50% v cci v cci v ol v oh isolation barrier fs low isolation barrier v i 50 w in v o input generator (1) c l (2) out 1.4 v 10% 90% v i v o t plh t phl 1.4 v v cci 0 v 50% t r t f v oh 50% v ol
iso7420e , iso7420fe , iso7421e , iso7421fe sllse45f ? december 2010 ? revised july 2015 www.ti.com 8 detailed description 8.1 overview the isolator in figure 19 is based on a capacitive isolation barrier technique. the i/o channel of the device consists of two internal data channels, a high-frequency channel (hf) with a bandwidth from 100 kbps up to 150 mbps, and a low-frequency channel (lf) covering the range from 100 kbps down to dc. in principle, a single- ended input signal entering the hf-channel is split into a differential signal via the inverter gate at the input. the following capacitor-resistor networks differentiate the signal into transients, which then are converted into differential pulses by two comparators. the comparator outputs drive a nor-gate flip-flop whose output feeds an output multiplexer. a decision logic (dcl) at the driving output of the flip-flop measures the durations between signal transients. if the duration between two consecutive transients exceeds a certain time limit, (as in the case of a low-frequency signal), the dcl forces the output-multiplexer to switch from the high- to the low- frequency channel. because low-frequency input signals require the internal capacitors to assume prohibitively large values, these signals are pulse-width modulated (pwm) with the carrier frequency of an internal oscillator, thus creating a sufficiently high frequency signal, capable of passing the capacitive barrier. as the input is modulated, a low-pass filter (lpf) is needed to remove the high-frequency carrier from the actual data before passing it on to the output multiplexer. 8.2 functional block diagram figure 19. conceptual block diagram of a digital capacitive isolator 16 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: iso7420e iso7420fe iso7421e iso7421fe
iso7420e , iso7420fe , iso7421e , iso7421fe www.ti.com sllse45f ? december 2010 ? revised july 2015 8.3 feature description iso742x are available in multiple channel configurations and default output state options to enable wide variety of application uses. product data rate default output rated t a channel direction iso7420e high same iso7420fe low 50 mbps ? 40 c to 125 c iso7421e high opposite iso7421fe low 8.3.1 insulation and safety-related specifications for d-8 package over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit l(i01) minimum air gap (clearance) shortest terminal-to-terminal distance through air 4 mm minimum external tracking shortest terminal-to-terminal distance across the l(i02) 4 mm (creepage) package surface tracking resistance (comparative cti din en 60112 (vde 0303-11); iec 60112 > 400 v tracking index) minimum internal gap (internal distance through the insulation 0.014 mm clearance) v io = 500 v, t a = 25 c > 10 12 ? isolation resistance, input to r io output (1) v io = 500 v, 100 c t a max > 10 11 ? barrier capacitance, input to c io v io = 0.4 sin (2 ft), f = 1 mhz 1 pf output (1) c i input capacitance (2) v i = v cc /2 + 0.4 sin (2 ft), f = 1 mhz, v cc = 5 v 1 pf (1) all pins on each side of the barrier tied together creating a two-terminal device. (2) measured from input pin to ground. note creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. creepage and clearance on a printed-circuit board become equal in certain cases. techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 17 product folder links: iso7420e iso7420fe iso7421e iso7421fe
iso7420e , iso7420fe , iso7421e , iso7421fe sllse45f ? december 2010 ? revised july 2015 www.ti.com 8.3.2 insulation characteristics over recommended operating conditions (unless otherwise noted) parameter (1) test conditions specification unit din v vde v 0884-10 (vde v 0884-10):2006-12 v iorm maximum workingisolation voltage 566 v peak method a, after environmental tests subgroup 1, v pr = v iorm x 1.6, t = 10 s, 906 partial discharge < 5 pc method b1, v pr input-to-output test voltage v pr = v iorm x 1.875, t = 1 s (100% production test) 1062 v peak partial discharge < 5 pc after input/output safety test subgroup 2/3, v pr = v iorm x 1.2, t = 10 s, 680 partial discharge < 5 pc v test = v iotm = 4242 v pk v iotm maximum transient isolation voltage t = 60 sec (qualification) 4242 v peak t= 1 sec (100% production) r s isolation resistance v io = 500 v at t s = 150 c > 10 9 ? pollution degree 2 ul 1577 v test = v iso = 2500 v rms , t = 60 sec (qualification); v iso maximum withstand isolation voltage 2500 v rms v test = 1.2 x v iso = 3000 v rms , t = 1 sec (100% production) (1) climatic classification 40/125/21 table 1. iec 60664-1 ratings table parameter test conditions specification basic isolation group material group ii rated mains voltage 150 v rms i ? iv installation classification rated mains voltage 300 v rms i ? iii 8.3.3 regulatory information vde csa ul cqc certified according to din v vde v 0884-10 (vde v 0884- approved under csa component recognized under ul 1577 certified according to gb 10):2006-12 and din en acceptance notice 5a, iec 60950-1, component recognition program 4943.1-2011 61010-1 (vde 0411-1):2011- and iec 61010-1 07 2500 v rms isolation rating; basic insulation per csa 60950-1- basic insulation; 07+a1 and iec 60950-1 2nd ed+a1, basic insulation, altitude maximum transient isolation 384 v rms maximum working voltage; single protection isolation voltage, 5000 m, tropical climate, 250 voltage, 4242 v pk ; csa 61010-1-04 and iec 61010-1 2500 v rms (1) v rms maximum working maximum working isolation 2nd ed, 300 v rms maximum working voltage voltage, 566 v pk voltage for basic insulation and 150 v rms for reinforced insulation certificate number: certificate number: 40016131 master contract number: 220991 file number: e181974 cqc14001109540 (1) production tested 3000 v rms for 1 second in accordance with ul 1577. 18 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: iso7420e iso7420fe iso7421e iso7421fe
iso7420e , iso7420fe , iso7421e , iso7421fe www.ti.com sllse45f ? december 2010 ? revised july 2015 8.3.4 life expectancy vs working voltage figure 20. life expectancy vs working voltage 8.3.5 safety limiting values safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. a failure of the i/o can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures. parameter test conditions min typ max unit ja = 212 c/w, v i = 5.5 v, t j = 150 c, t a = 25 c 107 safety input, output, or supply i s ma current ja = 212 c/w, v i = 3.6 v, t j = 150 c, t a = 25 c 164 t s maximum safety temperature 150 c the safety-limiting constraint is the absolute-maximum junction temperature specified in the absolute maximum ratings (1) table. the power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. the assumed junction-to-air thermal resistance in the thermal information table is that of a device installed in the jesd51-3, low-effective-thermal-conductivity test board for leaded surface-mount packages and is conservative. the power is the recommended maximum input voltage times the current. the junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. figure 21. jc thermal derating curve per vde (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 19 product folder links: iso7420e iso7420fe iso7421e iso7421fe case temperature ? c 0 20 40 60 80 100 120 140 160 180 0 50 100 150 200 safety limiting current ? ma v cc1 , v cc2 at 3.6 v v cc1 , v cc2 at 5.5 v 10 100 0 250 500 750 1000 v C working voltage C v iorm pk life expectancy C years 880 120 v at 566 v iorm 28 years g001
iso7420e , iso7420fe , iso7421e , iso7421fe sllse45f ? december 2010 ? revised july 2015 www.ti.com 8.4 device functional modes table 2. functional table (1) output input outa, outb v cci v cco ina, inb iso7420e / iso7421e iso7420fe / iso7421fe h h h pu pu l l l open h (2) l (3) pd pu x h (2) l (3) x pd x undetermined undetermined (1) v cci = input-side v cc ; v cco = output-side v cc ; pu = powered up (v cc 3 v); pd = powered down (v cc 2.1 v); x = irrelevant; h = high level; l = low level; (2) in fail-safe condition, output defaults to high level (3) in fail-safe condition, output defaults to low level 8.4.1 device i/o schematic figure 22. device i/o schematics 20 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: iso7420e iso7420fe iso7421e iso7421fe in 1 m w 500 w iso742xfx input v cci out 8 w 13 w output v cco v cci in 1 m w 500 w iso742xe input v cci v cci v cci
iso7420e , iso7420fe , iso7421e , iso7421fe www.ti.com sllse45f ? december 2010 ? revised july 2015 9 applications and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information iso742x utilize single-ended ttl-logic switching technology. its supply voltage range is from 3 v to 5.5 v for both supplies, v cc1 and v cc2 . when designing with digital isolators, it is important to keep in mind that due to the single-ended design structure, digital isolators do not conform to any specific interface standard and are only intended for isolating single-ended cmos or ttl digital signal lines. the isolator is typically placed between the data controller (i.e. c or uart), and a data converter or a line transceiver, regardless of the interface type or standard. 9.2 typical application iso7421 can be used with texas instruments' mixed signal micro-controller, digital-to-analog converter, transformer driver, and voltage regulator to create an isolated 4-20 ma current loop. figure 23. isolated 4-20 ma current loop copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 21 product folder links: iso7420e iso7420fe iso7421e iso7421fe iso7421 v cc1 v cc2
iso7420e , iso7420fe , iso7421e , iso7421fe sllse45f ? december 2010 ? revised july 2015 www.ti.com typical application (continued) 9.2.1 design requirements unlike optocouplers, which require external components to improve performance, provide bias, or limit current, the iso742x only require two external bypass capacitors to operate. 9.2.2 detailed design procedure 9.2.2.1 maximum supply current equations (calculated over recommended operating temperature range and silicon process variation) 9.2.2.1.1 iso7420 at v cc1 = v cc2 = 3.3v 10% i cc1 (max) = i cc1_q (max) + 1.791 x 10 -2 x f (1) i cc2 (max) = i cc2_q (max) + 1.687 x 10 -2 x f + 3.570 x 10 -3 x f x c l (2) at v cc1 = v cc2 = 5v 10% i cc1 (max) = i cc1_q (max) + 3.152 x 10 -2 x f (3) i cc2 (max) = i cc2_q (max) + 2.709 x 10 -2 x f + 5.365 x 10 -3 x f x c l (4) 9.2.2.1.2 iso7421 at v cc1 = v cc2 = 3.3v 10% i cc1 (max) = i cc1_q (max) + 1.726 x 10 -2 x f + 1.785 x 10 -3 x f x c l (5) i cc2 (max) = i cc2_q (max) + 1.726 x 10 -2 x f + 1.785 x 10 -3 x f x c l (6) at v cc1 = v cc2 = 5v 10% i cc1 (max) = i cc1_q (max) + 2.920 x 10 -2 x f + 2.682 x 10 -3 x f x c l (7) i cc2 (max) = i cc2_q (max) + 2.920 x 10 -2 x f + 2.682 x 10 -3 x f x c l (8) i cc1_q (max) and i cc2_q (max) are equivalent to the maximum supply currents measured in ma under dc input conditions (provided in the specification tables of this data sheet); f is data rate in mbps of both channels; c l is the capacitive load in pf of both channels. i cc1 (max) and i cc2 (max) are measured in ma. 9.2.2.2 typical supply current equations: (calculated over recommended operating temperature range and silicon process variation) 9.2.2.2.1 iso7420 at v cc1 = v cc2 = 3.3v i cc1 (typ) = i cc1_q (typ) + 1.528 x 10 -2 x f (9) i cc2 (typ) = i cc2_q (typ) + 1.637 x 10 -2 x f + 3.275 x 10 -3 x f x c l (10) at v cc1 = v cc2 = 5v i cc1 (typ) = i cc1_q (typ) + 2.640 x 10 -2 x f (11) i cc2 (typ) = i cc2_q (typ) + 2.502 x 10 -2 x f + 4.919 x 10 -3 x f x c l (12) 9.2.2.2.2 iso7421 at v cc1 = v cc2 = 3.3v i cc1 (typ) = i cc1_q (typ) + 1.567 x 10 -2 x f + 1.640 x 10 -3 x f x c l (13) i cc2 (typ) = i cc2_q (typ) + 1.567 x 10 -2 x f + 1.640 x 10 -3 x f x c l (14) at v cc1 = v cc2 = 5v i cc1 (typ) = i cc1_q (typ) + 2.550 x 10 -2 x f + 2.416 x 10 -3 x f x c l (15) i cc2 (typ) = i cc2_q (typ) + 2.550 x 10 -2 x f + 2.461 x 10 -3 x f x c l (16) 22 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: iso7420e iso7420fe iso7421e iso7421fe
iso7420e , iso7420fe , iso7421e , iso7421fe www.ti.com sllse45f ? december 2010 ? revised july 2015 typical application (continued) i cc1_q (typ) and i cc2_q (typ) are equivalent to the typical supply currents measured in ma under dc input conditions (provided in the specification tables of this data sheet); f is data rate in mbps of each channel; c l is the capacitive load in pf of each channel. i cc1 (typ) and i cc2 (typ) are measured in ma. figure 24. typical iso7420 circuit hookup figure 25. typical iso7421 circuit hookup copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 23 product folder links: iso7420e iso7420fe iso7421e iso7421fe 12 34 87 65 ina inb outa outb v cc2 0.1 f gnd2 0.1 f v cc1 gnd1 12 34 87 65 ina inb outa v cc2 0.1 f gnd2 0.1 f v cc1 outb gnd1
iso7420e , iso7420fe , iso7421e , iso7421fe sllse45f ? december 2010 ? revised july 2015 www.ti.com typical application (continued) 9.2.3 application curves figure 27. iso7420fe typical eye diagram at 100 mbps, figure 26. iso7420fe typical eye diagram at 50 mbps, 3.3 v operation 3.3 v operation 10 power supply recommendations to ensure reliable operation at all data rates and supply voltages, a 0.1 f bypass capacitor is recommended at input and output supply pins (v cc1 and v cc2 ). the capacitors should be placed as close to the supply pins as possible. if only a single primary-side power supply is available in an application, isolated power can be generated for the secondary-side with the help of a transformer driver such as texas instruments' sn6501 . for such applications, detailed power supply design and transformer selection recommendations are available in sn6501 datasheet ( sllsea0 ). 24 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: iso7420e iso7420fe iso7421e iso7421fe t = 25c, v = v = 3.3 v, a cc1 cc2 pattern: prbs 2 -1 7 t = 25c, v 1 = v 2 = 3.3 v, pattern: prbs 2 -1 a cc cc 7
iso7420e , iso7420fe , iso7421e , iso7421fe www.ti.com sllse45f ? december 2010 ? revised july 2015 11 layout 11.1 layout guidelines a minimum of four layers is required to accomplish a low emi pcb design (see figure 28 ). layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency signal layer. ? routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits of the data link. ? placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmission line interconnects and provides an excellent low-inductance path for the return current flow. ? placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately 100pf/in 2 . ? routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias. if an additional supply voltage plane or signal layer is needed, add a second power / ground plane system to the stack to keep it symmetrical. this makes the stack mechanically stable and prevents it from warping. also the power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly. for detailed layout recommendations, see application note digital isolator design guide , slla284 . 11.1.1 pcb material for digital circuit boards operating below 150 mbps, (or rise and fall times higher than 1 ns), and trace lengths of up to 10 inches, use standard fr-4 epoxy-glass as pcb material. fr-4 (flame retardant 4) meets the requirements of underwriters laboratories ul94-v0, and is preferred over cheaper alternatives due to its lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its self- extinguishing flammability-characteristics. 11.2 layout example figure 28. recommended layer stack copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 25 product folder links: iso7420e iso7420fe iso7421e iso7421fe 10 mils 10 mils 40 mils fr-4 0 r ~ 4.5 keep this space free from planes, traces , pads, and vias ground plane power plane low-speed traces high-speed traces
iso7420e , iso7420fe , iso7421e , iso7421fe sllse45f ? december 2010 ? revised july 2015 www.ti.com 12 device and documentation support 12.1 documentation support 12.1.1 related documentation for related documentation see the following: ? sn6501 transformer driver for isolated power supplies , sllsea0 ? isolation glossary , slls353 12.2 related links the table below lists quick access links. categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. table 3. related links technical tools & support & parts product folder sample & buy documents software community iso7420e click here click here click here click here click here iso7420fe click here click here click here click here click here iso7421e click here click here click here click here click here iso7421fe click here click here click here click here click here 12.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.4 trademarks devicenet, e2e are trademarks of texas instruments. all other trademarks are the property of their respective owners. 12.5 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 12.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 13 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. 26 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: iso7420e iso7420fe iso7421e iso7421fe
package option addendum www.ti.com 21-may-2013 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) op temp (c) device marking (4/5) samples iso7420ed active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 so7420 iso7420edr active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 so7420 iso7420fed active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 i7420f iso7420fedr active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 i7420f iso7421ed active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 so7421 iso7421edr active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 so7421 iso7421fed active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 i7421f iso7421fedr active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 i7421f (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature.
package option addendum www.ti.com 21-may-2013 addendum-page 2 (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of iso7421e : ? automotive: iso7421e-q1 note: qualified version definitions: ? automotive - q100 devices qualified for high-reliability automotive applications targeting zero defects
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant iso7420edr soic d 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 q1 iso7420fedr soic d 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 q1 iso7421edr soic d 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 q1 iso7421fedr soic d 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 q1 package materials information www.ti.com 23-nov-2013 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) iso7420edr soic d 8 2500 367.0 367.0 35.0 iso7420fedr soic d 8 2500 367.0 367.0 35.0 iso7421edr soic d 8 2500 367.0 367.0 35.0 iso7421fedr soic d 8 2500 367.0 367.0 35.0 package materials information www.ti.com 23-nov-2013 pack materials-page 2

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